1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device and a method for manufacturing the same, which is capable of reducing bubble defects.
2. Description of the Related Art
In general, a high-density plasma (HDP) oxide layer having a high step coverage property is used primarily as an insulating layer for filling gaps between patterns. Since a high temperature flow process is not required for the HDP oxide layer after deposition, the HDP oxide layer has been used as an interlayer dielectric (ILD) film.
FIG. 1 illustrates a sectional view of a semiconductor device in which a HDP oxide layer is used as an ILD film for filling a gap between gate electrodes.
Referring to FIG. 1, a gate insulating layer 12, a doped polysilicon layer 14, a metal silicide layer 16, and a capping insulating layer 18, are sequentially stacked on a semiconductor substrate 10. Next, a portion of the capping insulating layer 18, a portion of the metal silicide layer 16, and a portion of the doped polysilicon layer 14 are patterned.
A spacer 20 is formed by a well-known method on both sidewalls of the patterned capping insulating layer 18, the patterned metal silicide layer 16, and the patterned doped polysilicon layer 14, thereby forming a gate electrode structure 22 including the gate insulating layer 12, the doped polysilicon layer 14, the metal silicide layer 16, the capping insulating layer 18, and the spacer 20.
A gate poly oxide (GPOX) layer 24 is deposited on the surface of the semiconductor substrate 10 on which the gate electrode structure 22 is formed. The GPOX layer 24 cures damage occurring in the patterning process for forming the gate electrode structure 22 by smoothing the edges of the gate electrode structure 22 and the surface of the semiconductor substrate 10, thereby preventing electrostatic fields from being concentrated on the edges of the gate electrode structure 22.
Next, impurity ions are implanted into the semiconductor substrate 10 at both sides of the gate electrode structure 22, thereby forming a junction region 26. An etch stopper 28 formed of silicon nitride (Si3N4) is deposited on the surface of the GPOX layer 24. Next, a HDP oxide layer 30 is deposited as an interlayer dielectric ((ILD) film.
However, a conventional semiconductor device has the following problems. In general, lifting occurs at an interface between silicon oxide (SiO2) and a lower material of silicon oxide (SiO2), and at an interface between silicon oxide (SiO2) and silicon nitride (Si3N4), when the HDP oxide layer is deposited on a structure on which thin layers of silicon oxide (SiO2) and silicon nitride (Si3N4) are sequentially stacked. The interfacial lifting is referred to as bubble defects. When depositing the HDP oxide layer, the bubble defects are caused by a difference in stress between silicon oxide (SiO2) and silicon nitride (Si3N4), or by outgassed hydrogen ions.
The bubble defects occur in the above-mentioned semiconductor device. That is, the HDP oxide layer 30 is formed on the semiconductor substrate 10 including a stack comprised of the GPOX layer 24 formed of silicon oxide (SiO2) and the etch stopper 28 formed of silicon nitride (Si3N4), and thus, the bubble defects occur.
Due to the bubble defects occurring in the semiconductor device, the adhesive strength of the interfaces is lowered, particles occur in the lift, and electrical properties of the semiconductor device are degraded.
In order to prevent the bubble defects, a method for relatively increasing the thickness of either the GPOX layer 24 or the etch stopper 28 has been suggested. However, in this case, the spacing between the gate electrode structures 22 is reduced, and thus a gap fill margin of the HDP layer 30 is reduced. Accordingly, the stress between the GPOX layer 24 and the etch stopper 28 is reduced.
In an effort to solve the above problem, it is a first feature of an embodiment of the present invention to provide a semiconductor device capable of reducing bubble defects in a gate electrode structure without reducing a gap fill margin of an interlayer dielectric (ILD) film.
It is a second feature of an embodiment of the present invention to provide a method for manufacturing a semiconductor device capable of reducing bubble defects.
Accordingly, to provide the first feature, according to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device. In the method, a gate electrode structure is formed on a surface of a semiconductor substrate. A gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on the semiconductor substrate. The surface of the semiconductor substrate is cleaned to remove any residue and the GPOX layer. An etch stopper is formed on the surface of the gate electrode structure and on the semiconductor substrate. A high-density plasma (HDP) oxide layer is deposited on the etch stopper.
The semiconductor substrate may be cleaned using a solution in which a buffer oxide etchant (BOE) (HF+NH4F) solution is mixed with a standard cleaning 1 (SC1) (NH4OH+H2O2+H2O) solution. Pre-processing the surface of the semiconductor substrate using a high temperature sulfuric acid solution may be further performed after forming the gate electrode structure and before cleaning the surface of the semiconductor substrate.
A preferred formation of the gate electrode structure will now be described. In the preferred formation, a gate insulating layer, a conductive layer, and a capping insulating layer are sequentially formed on the semiconductor substrate. The capping insulating layer and the conductive layer are patterned. A spacer is formed on both sidewalls of the capping insulating layer and the conductive layer. In this case, after patterning the capping insulating layer and the conductive layer and before forming the spacer on both sidewalls of the capping insulating layer and the conductive layer, low concentration impurity ions are implanted into the semiconductor substrate at both sides of the patterned capping insulating layer and the patterned conductive layer. In addition, after forming the spacer, high concentration impurity ions are implanted into the semiconductor substrate at both sides of the spacer.
Further, after patterning the capping insulating layer and the conductive layer and before implanting low concentration impurity ions into the semiconductor substrate, an intermediate GPOX layer is additionally formed on the surface of the semiconductor substrate and on the surface of the conductive layer. The intermediate GPOX layer additionally formed is formed by a thermal oxidation method.
To provide the first feature, according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device.
A gate electrode structure is formed on a surface of a semiconductor substrate. An etch stopper is formed on the surface of the gate electrode structure and on the semiconductor substrate. A high-density plasma (HDP) oxide layer is deposited on the etch stopper.
After forming the gate electrode structure and before forming the etch stopper, the surface of the semiconductor substrate may be cleaned.
To provide the second feature, there is provided a semiconductor device. The semiconductor device includes a semiconductor substrate, a gate electrode structure formed on the semiconductor substrate, an etch stopper covering the semiconductor substrate and a surface of the gate electrode structure, and a high-density plasma (HDP) oxide layer formed on the etch stopper.